Unit Overview

Processor fundamentals

CIE A-Level Computer Science· 5 min read 📊 n/a

1. Unit at a glance

This unit builds incrementally from basic CPU operation to advanced performance-enhancing design choices. You will start with the core components of the processor and the standard fetch-decode-execute cycle, then move on to how instructions are structured and how they access data. We then compare the two dominant processor architecture paradigms before covering two key techniques used to boost processing speed: pipelining and multicore design.

Work through the sub-topics below in order to build your understanding step-by-step:

CPU structure and function

Covers core CPU components, the fetch-decode-execute cycle, and CPU-memory interaction.

★★⏱ 10 min

Instruction set

Explains instruction sets, machine code vs assembly, and common categories of instructions.

★★⏱ 8 min

Addressing modes

Covers common methods for accessing operands stored in registers or memory.

★★★⏱ 7 min

RISC vs CISC

Compares design characteristics, advantages, and disadvantages of RISC and CISC architectures.

★★★⏱ 6 min

Pipelining

Explains how pipelining improves throughput and covers common pipeline hazards.

★★★★⏱ 9 min

Multicore processors

Explores multicore performance benefits, Amdahl's law, and parallel processing challenges.

★★★⏱ 8 min

2. Common Pitfalls

Wrong move:

Confusing clock frequency with overall processor performance

Why:

Students often assume higher clock speed always equals faster performance, ignoring the impact of architecture, pipelining and core count.

Correct move:

Evaluate performance based on all design factors, not just clock speed, when comparing different processors.

Wrong move:

Thinking RISC is always superior to CISC for every use case

Why:

RISC advantages are context-dependent, and CISC remains widely used for many specific applications.

Correct move:

Compare RISC and CISC based on use case, power constraints, and design goals, not just a blanket ranking.

Wrong move:

Confusing pipelining with multicore processing

Why:

Both improve performance but work via fundamentally different mechanisms.

Correct move:

Remember: pipelining overlaps instruction execution on a single core, while multicore uses separate cores for parallel execution.

3. Quick Reference Cheatsheet

Concept	Key Definition / Formula
Fetch-Decode-Execute Cycle	Fetch instruction 2. Decode opcode 3. Fetch operands 4. Execute 5. Store result
CPI	Cycles Per Instruction: Average number of clock cycles required to execute one instruction
Immediate Addressing	Operand value is stored directly in the instruction itself
RISC Core Traits	Fixed-length instructions, large register set, simple instructions, compiler-dependent optimization
CISC Core Traits	Variable-length instructions, complex instructions, smaller register set, hardware-implemented complex operations
Pipeline Speedup (ideal)	Speedup = Number of pipeline stages for a fully loaded pipeline
Amdahl's Law	Speedup = $\frac{1}{( 1 - P ) + \frac{P}{N}}$ , where $P$ = parallelizable proportion of code, $N$ = number of cores

What's Next

Start your learning for this unit by exploring the first sub-topic on CPU structure and function. Work through each sub-topic in order to build your understanding incrementally from basic operation to advanced performance optimizations. Once you complete all topics in this unit, you can move on to the next unit covering memory and storage fundamentals.