RISC vs CISC

Computer Science· Unit 4: Processor Fundamentals· 45 min read

1. Core Design Principles★★☆☆☆⏱ 10 min

RISC and CISC originated from competing approaches to trade-offs between instruction complexity and hardware efficiency. Early computing had limited memory, so CISC was designed to reduce program size by making individual instructions more powerful.

📘 Definition

RISC Design Philosophy

RISC prioritises simple instructions that execute in a single clock cycle. The goal is to reduce CPI and enable efficient pipelining, with compilers handling more instruction-level work.

Example:

A RISC ISA splits a complex memory-to-memory add into three separate simple instructions: load, add, store.

CISC, by contrast, builds complex operations directly into the instruction set to reduce the number of instructions a program needs to execute.

📐 Worked Example

Show how adding two memory-resident numbers would be implemented in RISC vs CISC

1
For CISC, the operation completes in a single instruction that accesses memory directly:
2
$ADD \quad [M_A], [M_B] \rightarrow [M_C]$
3
For RISC, all operations must act on registers, so the operation is split into four simple instructions:
4
$\begin{aligned} \text{LOAD } R1, [M_A] \\ \text{LOAD } R2, [M_B] \\ \text{ADD } R3, R1, R2 \\ \text{STORE } [M_C], R3 \end{aligned}$

Exam tip:

For comparison questions in CIE exams, always structure answers by pairing characteristics for each architecture to get full marks.

2. Key Architectural Differences★★★☆☆⏱ 15 min

Beyond core philosophy, RISC and CISC differ in several key hardware and software characteristics that impact overall performance.

Characteristic	RISC	CISC
Instruction set size	Small ~100-200 instructions	Large ~200-1000+ instructions
Instruction length	Fixed	Variable
Average CPI	~1	1-15+ (variable)
General purpose registers	Large count (16+)	Smaller count (8-16)
Memory access rules	Only load/store access memory	All instructions can access memory
Pipelining efficiency	Easy to implement efficiently	More complex due to variable instructions
Compiler complexity	More complex	Simpler

📐 Worked Example

Identify which feature is characteristic of RISC: (A) Variable instruction length (B) Single cycle per instruction (C) Direct memory access for arithmetic (D) Small number of registers. State the correct answer and eliminate incorrect options.

1
Correct answer is (B). RISC design prioritises simple instructions that complete in one clock cycle.
2
Eliminate (A): RISC uses fixed-length instructions to simplify pipelining; variable length is a CISC feature.
3
Eliminate (C): Only load/store instructions can access memory in RISC; arithmetic operations only use registers.
4
Eliminate (D): RISC has a large number of general purpose registers to reduce memory access; small register count is CISC.

3. Performance and Design Trade-offs★★★☆☆⏱ 12 min

The choice between RISC and CISC depends on performance goals, memory constraints, power consumption, and hardware complexity requirements.

RISC benefits: Lower power consumption, efficient pipelining, higher instruction throughput, simpler hardware
RISC drawbacks: Larger program size, more complex compiler, overhead from splitting complex operations
CISC benefits: Smaller program size, lower memory bandwidth usage, simpler compiler output
CISC drawbacks: Higher hardware complexity, higher power consumption, harder to pipeline efficiently

📐 Worked Example

Explain why RISC processors are preferred for mobile phones, while CISC is common in desktop PCs

1
Mobile phones prioritise low power consumption and energy efficiency, which aligns with RISC design principles.
2
RISC's simple hardware and efficient pipelining produce less heat and use less battery, a critical requirement for mobile devices.
3
Desktop PCs historically used CISC (x86) to maintain backward compatibility with older software, and benefit from the large memory available in modern systems.
4
Modern desktop CPUs use RISC-like internal micro-operations but retain the CISC instruction set for compatibility, so they are still classified as CISC.

4. Real-World Examples & Exam Phrasing★★☆☆☆⏱ 8 min

In modern computing, both architectures are widely used for their intended use cases. These are the common examples you are expected to know for CIE exams:

RISC examples: ARM (all mobile phones, Raspberry Pi), RISC-V, MIPS
CISC examples: x86/x86-64 (most desktops/laptops/servers), VAX, Intel 80x86

📐 Worked Example

Name one RISC and one CISC processor example, and state their typical use case

1
RISC example: ARM Cortex-A series
2
Use case: Smartphones and tablets, where low power consumption is a critical requirement
3
CISC example: Intel Core i7 (x86 architecture)
4
Use case: Desktop and laptop PCs, where backward compatibility and general purpose performance are prioritised

✓ Quick check

Test your understanding of use cases:

Which of these processors is a RISC architecture?
- Intel Core i7
- AMD Ryzen
- ARM Cortex-A
- x86-64
Reveal answer
2 —
Correct: ARM is the most widely used RISC architecture today. Intel and AMD x86 are CISC architectures.
Why is RISC suitable for embedded systems?
- Small program size
- Low power consumption
- Complex instructions
- Backward compatibility
Reveal answer
1 —
Correct: RISC's simple hardware design leads to low power consumption, ideal for battery-powered embedded and mobile systems.

5. Common Pitfalls

Wrong move:

Claiming CISC always has higher performance than RISC because individual instructions are more powerful

Why:

CPI is much higher for CISC, so overall instruction throughput is often lower than RISC for most workloads

Correct move:

Compare the full trade-off: CISC has lower instruction count but higher CPI; RISC has higher instruction count but lower average CPI

Wrong move:

Thinking all modern desktop CPUs are pure CISC designs

Why:

Modern x86 CPUs translate CISC instructions to internal RISC-like micro-operations before execution

Correct move:

Recognise x86 is a hybrid, but still classified as CISC from an ISA perspective for exam purposes

Wrong move:

Claiming RISC has fewer registers than CISC

Why:

RISC uses more registers to avoid repeated memory access for operands, a core design feature

Correct move:

RISC has a larger number of general purpose registers than CISC

Wrong move:

Confusing which architecture requires more complex compiler work

Why:

Because RISC splits complex operations into multiple simple instructions, the compiler must do more work

Correct move:

RISC = more complex compiler; CISC = simpler compiler

6. Quick Reference Cheatsheet

Characteristic	RISC	CISC
Instruction length	Fixed	Variable
Average CPI	~1	Variable 1+
Memory access	Load/store only	Direct for all instructions
General purpose registers	Many	Fewer
Pipelining efficiency	High	Lower
Compiler complexity	Complex	Simple
Power consumption	Lower	Higher
Common examples	ARM, RISC-V	x86, x86-64

When this came up on past exams

AI-estimated based on syllabus patterns — cross-check with official past papers for accuracy. Use only as revision-focus signals.

2022 · 41
Compare RISC and CISC features
2020 · 42
Explain RISC pipelining benefit

Going deeper

syllabusCIE 9618 Syllabus Page

What's Next

Understanding RISC and CISC is fundamental to further study of CPU performance, pipelining, and embedded system design. This topic frequently appears in CIE exam questions asking you to compare architectural choices for different computing devices, so always ensure you can link specific design features to performance outcomes and use case requirements. Mastery of this topic also provides a foundation for understanding modern hybrid CPU designs that combine elements of both philosophies.