CPU Structure and Function
Computer ScienceΒ· Unit 4: Processor fundamentals, Topic 1Β· 25 min read
1. Main CPU Components and Their Functionsβ β ββββ± 8 min
The CPU (Central Processing Unit) is the core processing component of a computer, responsible for executing all program instructions. It has three core building blocks: the Arithmetic Logic Unit (ALU), Control Unit (CU), and on-board registers.
Arithmetic Logic Unit (ALU)
The CPU component that performs all arithmetic operations (addition, subtraction, multiplication) and logical operations (AND, OR, NOT, comparisons) required for instruction execution.
Example:
Adding two values stored in registers, or checking if one number is greater than another.
The Control Unit (CU) coordinates all activity across the CPU. It decodes fetched instructions and sends control signals to other components to trigger the required action. Registers are small, high-speed memory locations built directly into the CPU, used to store data and addresses that are being processed immediately.
A student claims the ALU is responsible for decoding instructions. Identify the error and state the correct roles of the main CPU components.
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Step 1: Identify the error: Decoding instructions is not a function of the ALU, it is a function of the Control Unit.
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Step 2: State the correct role of each core component:
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- ALU: Performs all arithmetic and logical operations on data
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- Control Unit: Decodes instructions and coordinates CPU activity
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- Registers: Store temporary data, addresses and instructions for immediate processing
Exam tip:
Always match each component to its correct function in diagram questions to earn full marks.
2. Special-Purpose CPU Registersβ β β βββ± 7 min
Registers are the fastest form of memory in a computer system, much faster than cache or RAM. Most registers have dedicated, specific roles during instruction execution, and CIE 9618 requires you to recall the function of the most common special-purpose registers.
Program Counter (PC)
A special register that holds the memory address of the next instruction to be fetched from main memory. It is automatically incremented after each fetch to point to the next instruction in sequence.
Memory Address Register (MAR): Holds the address of the memory location the CPU wants to read from or write to.
Memory Data Register (MDR): Holds the data that was just read from memory, or data waiting to be written to memory.
Current Instruction Register (CIR): Holds the current instruction that has just been fetched and is waiting to be decoded.
Accumulator (ACC): Stores intermediate results of calculations performed by the ALU.
Explain the difference between the role of the MAR and MDR when the CPU reads data from main memory. Use an example to illustrate.
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Step 1: Clarify the role of the MAR: The MAR only stores the address of the memory location the CPU needs to access, it never stores the actual data.
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Step 2: Clarify the role of the MDR: After the address is sent to main memory from the MAR, the data at that address is returned and stored in the MDR for processing.
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Step 3: Example: If the CPU needs to read an instruction stored at memory address $20A, the address $20A is loaded into the MAR. The instruction stored at $20A is retrieved from memory and stored in the MDR, ready to be decoded.
3. System Busesβ β ββββ± 5 min
Buses are shared communication pathways that transfer data and control signals between CPU components, and between the CPU and main memory. There are three main types of system bus, each with a dedicated function and direction of travel.
System Bus
The collective term for the three main buses that connect the CPU to main memory and other peripherals.
Address Bus: Carries memory addresses from the CPU to main memory. It is unidirectional (only flows from CPU to memory).
Data Bus: Carries actual data between the CPU and main memory. It is bidirectional (data flows both ways).
Control Bus: Carries control signals from the CU to other components (e.g. read/write signals). It is bidirectional to allow status signals to return to the CPU.
A bus carries a signal indicating that the CPU wants to write data to a specific memory location. What type of bus is this? Explain why it is not the other two bus types.
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Step 1: Identify the signal type: This is a control signal that indicates the type of operation the CPU is performing.
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Step 2: Match to the correct bus type: This signal is carried by the control bus.
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Step 3: Explain why it is not other bus types: The address bus only carries memory addresses, not control signals. The data bus only carries the actual data being transferred, so neither carry operation type signals.
4. The Fetch-Decode-Execute Cycleβ β β βββ± 5 min
The fetch-decode-execute cycle is the repeating process the CPU follows for every program instruction. It runs continuously from system boot until shutdown, processing one instruction per full cycle (in a basic non-pipelined CPU).
Fetch-Decode-Execute Cycle
The sequential process the CPU uses to retrieve, decode and execute every program instruction from main memory.
Outline the complete sequence of steps for one full fetch-decode-execute cycle in a basic CPU.
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Fetch Step 1: The address stored in the Program Counter (PC) is copied to the Memory Address Register (MAR)
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Fetch Step 2: The instruction at the address in the MAR is fetched from main memory into the Memory Data Register (MDR)
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Fetch Step 3: The PC is incremented by 1 to point to the address of the next instruction to be fetched
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Decode Step 1: The instruction from the MDR is copied to the Current Instruction Register (CIR)
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Decode Step 2: The Control Unit decodes the instruction's opcode to determine what action is required
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Execute Step: The Control Unit sends control signals to relevant components to execute the instruction, with any results stored in the accumulator or registers
Exam tip:
When asked to describe this cycle, always mention the role of each register in each step to access full marks.
5. Common Pitfalls
Wrong move:
Claiming the Program Counter holds the current instruction, not the address of the next instruction
Why:
Common confusion between the roles of the PC and Current Instruction Register
Correct move:
PC = address of next instruction; CIR = holds the current instruction being decoded
Wrong move:
Saying the address bus is bidirectional or the data bus is unidirectional
Why:
Widely tested mix-up between bus direction properties
Correct move:
Address bus = unidirectional (CPU β memory); Data bus = bidirectional (CPU β memory)
Wrong move:
Claiming the MDR holds memory addresses
Why:
Persistent confusion between the roles of MAR and MDR
Correct move:
MAR holds memory addresses; MDR holds the actual data/instructions retrieved from that address
Wrong move:
Forgetting to mention incrementing the PC after the fetch step
Why:
Candidates often miss this step in exam answers, losing easy marks
Correct move:
Always explicitly state that the PC is incremented after fetching to point to the next instruction
Wrong move:
Stating the ALU decodes instructions
Why:
Common mix-up between the roles of the ALU and Control Unit
Correct move:
Control Unit decodes instructions; ALU performs arithmetic and logical operations
6. Quick Reference Cheatsheet
Component | Core Function |
|---|---|
ALU | Performs arithmetic and logical operations |
Control Unit | Decodes instructions, coordinates CPU activity |
PC | Holds address of next instruction to fetch |
MAR | Holds address of memory location to access |
MDR | Holds data/instructions read from/written to memory |
CIR | Holds current instruction being decoded |
ACC | Stores intermediate calculation results |
Address Bus | Carries memory addresses, unidirectional |
Data Bus | Carries actual data, bidirectional |
Control Bus | Carries control signals, bidirectional |
When this came up on past exams
AI-estimated based on syllabus patterns β cross-check with official past papers for accuracy. Use only as revision-focus signals.
- 2022 Β· 12
Describe core CPU components
- 2023 Β· 11
Explain fetch-decode-execute cycle
- 2024 Β· 12
Compare system bus types
Going deeper
What's Next
Understanding CPU structure and function is the foundational knowledge for all processor fundamentals topics, and is almost always tested in Paper 1 of CIE 9618, typically as a 4-6 mark short answer question. Mastery of the register roles and fetch-decode-execute sequence covered here is essential to understand more advanced performance optimisation topics that build on this foundation. Next you will explore differences between CISC and RISC CPU designs, how cache memory improves CPU access speed, and how pipelining and parallel processing increase instruction throughput.