Computer Architecture
Computer ScienceΒ· 15 min read
1. Core CPU Componentsβ β ββββ± 4 min
Central Processing Unit (CPU)
The core component of a computer that executes program instructions by performing arithmetic, logical, and input/output operations
Example:
A quad-core Intel i5 CPU contains four independent processing units
The CPU is structured into three core interconnected components, each with a distinct role in instruction processing:
- Arithmetic Logic Unit (ALU): Performs all arithmetic (addition, subtraction) and logical (AND, OR, NOT) operations on data
- Control Unit (CU): Coordinates CPU activity, fetches instructions from memory, decodes them, and controls data flow between components
- Registers: Super-fast on-CPU memory locations that store temporary data and instructions for immediate use
State one role each of the ALU and Control Unit in a CPU
- 1
First, match each component to its core function:
- 2
The ALU is responsible for calculations and logical comparisons. A valid role is: Performs addition when calculating the sum of two user input numbers
- 3
The Control Unit coordinates all CPU activity. A valid role is: Coordinates the fetching of the next program instruction from main memory
Exam tip:
Always include a specific, concrete example when asked for a component's role to earn full marks in CIE exams
2. Key CPU Registers and Their Rolesβ β β βββ± 5 min
CIE exams regularly ask candidates to name and explain the function of the 5 core special-purpose CPU registers used during the fetch-decode-execute cycle.
Register Name | Abbreviation | Core Function |
|---|---|---|
Program Counter | PC | Stores the memory address of the next instruction to fetch |
Memory Address Register | MAR | Stores the address of the memory location to access |
Memory Data Register | MDR | Stores the data fetched from or to be written to memory |
Current Instruction Register | CIR | Stores the current instruction being decoded/executed |
Accumulator | ACC | Stores intermediate results of ALU operations |
A CPU is about to read data from memory location 0x2A. Which register holds the address 0x2A, and what is the role of the MDR after the read completes?
- 1
First, match the question requirement to the function of each register:
- 2
Addresses of memory locations to be accessed are stored in the Memory Address Register (MAR). So address 0x2A is held in the MAR.
- 3
After the read completes, the data retrieved from memory location 0x2A is transferred to the MDR, which temporarily stores this data before it is processed by the CPU.
3. Von Neumann Architectureβ β ββββ± 3 min
Von Neumann Architecture
A computer architecture design where both program instructions and data are stored in the same shared main memory, and use the same system bus
Example:
Most general-purpose personal computers use a von Neumann architecture
The key defining feature of von Neumann architecture is shared access to memory and the system bus for both instructions and data. This design is simple and flexible for general-purpose computing, but creates a performance limit called the von Neumann bottleneck.
Explain why the von Neumann bottleneck occurs
- 1
Recall the core structure of von Neumann architecture: instructions and data share the same main memory and same system bus.
- 2
Only one transfer (either an instruction or a piece of data) can occur over the shared bus at any one time.
- 3
Modern CPUs can process data much faster than the bus can transfer instructions and data, so the bus becomes a bottleneck that limits overall system performance.
4. Harvard Architecture and Comparisonβ β β βββ± 3 min
Harvard Architecture
A computer architecture design that uses separate physical memory areas and separate buses for program instructions and data
Example:
Microcontrollers and GPUs typically use Harvard architecture
Harvard architecture eliminates the von Neumann bottleneck because instructions and data can be fetched in parallel over separate buses. It is most commonly used in embedded systems and graphics processing where consistent high performance is prioritized over flexibility.
State one similarity, one difference and one use case each for von Neumann and Harvard architectures
- 1
Similarity: Both architectures use a CPU with an ALU, Control Unit, and registers to process instructions and data.
- 2
Key difference: Von Neumann uses a single shared memory and bus for instructions and data, while Harvard uses separate memory and separate buses for each.
- 3
Use case (von Neumann): General-purpose desktop and laptop computers, where flexibility for variable program sizes and data requirements is critical.
- 4
Use case (Harvard): Embedded microcontrollers in household appliances, where the instruction set is fixed and fast, predictable execution is required.
Exam tip:
CIE almost always includes a comparison question on these two architectures, so memorize their differences and common use cases
5. Common Pitfalls
Wrong move:
Claiming the Program Counter (PC) stores the current instruction being executed
Why:
Students commonly confuse the PC and the Current Instruction Register (CIR)
Correct move:
The PC stores the memory address of the next instruction to fetch; the CIR stores the actual current instruction being executed
Wrong move:
Mixing up the roles of the MAR and MDR
Why:
The similar names lead students to confuse which holds addresses and which holds data
Correct move:
MAR = Memory Address Register, holds addresses of memory locations; MDR = Memory Data Register, holds the actual data from those locations
Wrong move:
Thinking registers are a type of main memory
Why:
Students confuse the hierarchy of memory types
Correct move:
Registers are located directly on the CPU chip, they are the fastest type of memory, not part of off-chip main RAM
Wrong move:
Claiming Harvard architecture is better than von Neumann for all use cases
Why:
Students focus only on the performance benefit of parallel fetching and ignore flexibility tradeoffs
Correct move:
Harvard is better for fixed-function embedded systems, while von Neumann is more flexible and better suited for general-purpose computing
6. Quick Reference Cheatsheet
Component/Register | Core Role | Von Neumann | Harvard |
|---|---|---|---|
ALU | Arithmetic/logical operations | Shared memory/bus for instructions/data | Separate memory/bus for instructions/data |
CU | Coordinates instruction processing | Suffers from von Neumann bottleneck | No bottleneck, parallel instruction/data fetch |
PC | Address of next instruction to fetch | Used in general-purpose PCs/laptops | Used in embedded systems, GPUs, microcontrollers |
MAR | Address of memory location to access | ||
MDR | Temporary storage for memory data | ||
CIR | Stores current instruction being processed | ||
Accumulator | Stores ALU intermediate results |
When this came up on past exams
AI-estimated based on syllabus patterns β cross-check with official past papers for accuracy. Use only as revision-focus signals.
- 2022 Β· 12
Compare von Neumann vs Harvard architecture
- 2023 Β· 11
Name 4 CPU registers and their roles
- 2021 Β· 13
Outline components of the von Neumann model
Going deeper
What's Next
Computer architecture is the foundational knowledge for understanding how CPUs execute instructions, and it underpins all further topics in hardware for CIE A-Level. This subtopic is a consistent source of easy short-answer marks on Paper 1, so mastering register roles and architecture comparisons is a high-impact study priority. Next, you will build on this knowledge to learn the step-by-step fetch-decode-execute cycle that uses all the registers and architectural features we covered here, before moving on to memory hierarchy and processor performance.