Computer Architecture — A-Level Computer Science Study Guide

For: A-Level Computer Science candidates sitting A-Level Computer Science.

Covers: Von Neumann architecture, core CPU components, fetch-decode-execute cycle, system bus types, RISC vs CISC architectures, and pipelining intuition as specified in the A-Level Computer Science syllabus.

You should already know: Basic programming concepts; one of Python / Java / VB.

A note on the practice questions: All worked questions in the "Practice Questions" section below are original problems written by us in the A-Level Computer Science style for educational use. They are not reproductions of past Cambridge International examination papers and may differ in wording, numerical values, or context. Use them to practise the technique; cross-check with official Cambridge mark schemes for grading conventions.

1. What Is Computer Architecture?

Computer architecture is the set of structural rules, operational protocols, and component interaction frameworks that define how a computer system processes, stores, and transfers data to execute program instructions. It is a core unit in A-Level Computer Science Paper 1, worth ~15% of total AS marks, and lays the foundation for all hardware-related topics in the full A-Level syllabus. Common synonyms include computer system organisation and hardware architecture, and exam questions will test both theoretical knowledge and practical application of performance tradeoffs.

2. Von Neumann architecture

Proposed by John von Neumann in 1945, this is the foundational design for almost all modern general-purpose computers, built around four core principles:

1. A single shared memory space stores both program instructions and user data, rather than separate memory banks for each
2. All instructions and data are encoded as binary values, with no physical distinction between the two in memory
3. Instructions are fetched sequentially from memory and executed by the central processing unit (CPU)
4. A single control unit manages all operation timing and component coordination via the fetch-decode-execute cycle

A key point examiners frequently test is the contrast between Von Neumann and Harvard architecture, the latter of which uses separate memory for instructions and data. For example, your laptop runs on Von Neumann design for flexibility, while a smart speaker embedded microcontroller uses Harvard architecture for faster parallel access to instructions and audio data.

Worked example: If you write a Python program to calculate the average of a list of numbers, both the code instructions (sum(list)/len(list)) and the numeric values in the list are stored in the same RAM chip, per Von Neumann rules. The CPU fetches the instruction first, then the data, from the same memory pool.

3. CPU components — ALU, CU, registers, cache

The CPU is the "brain" of the computer, responsible for executing all program instructions, and is made of four core subcomponents you must name and describe for exam questions:

1. Arithmetic Logic Unit (ALU): Performs all arithmetic operations (addition, subtraction, multiplication, division) and logical operations (AND, OR, NOT, equality/inequality comparisons like x > 5). Intermediate results are stored temporarily in the accumulator to avoid slow repeated writes to RAM.
2. Control Unit (CU): Coordinates all CPU operations by sending timed control signals to other components. It manages the fetch-decode-execute cycle, prioritises hardware requests, and prevents bus conflicts between components.
3. Registers: Ultra-fast, small temporary storage locations inside the CPU that hold data and instructions being actively processed. The five registers specified in the A-Level syllabus are:

• Program Counter (PC): Holds the memory address of the next instruction to be fetched
• Memory Address Register (MAR): Holds the address of the memory location the CPU wants to read from or write to
• Memory Data Register (MDR): Holds data fetched from memory, or data waiting to be written to memory
• Current Instruction Register (CIR): Holds the instruction currently being decoded and executed
• Accumulator (ACC): Stores intermediate results from ALU operations

4. Cache: High-speed memory sitting between the CPU and RAM that stores frequently used instructions and data to reduce the number of slow RAM accesses. Cache is tiered: L1 (smallest, fastest, per CPU core), L2, L3 (larger, slightly slower, shared between cores). A cache hit (data found in cache) takes ~1ns to access, while a cache miss (data fetched from RAM) takes ~100ns, so larger cache sizes significantly improve performance for repetitive tasks.

Worked example: When executing the calculation 4 * 7 + 3, the ALU first computes 4*7=28 and stores 28 in the accumulator, then adds 3 to the accumulator value to get 31, before writing the final result to RAM. This avoids writing the intermediate value 28 to RAM, saving ~100ns of latency.

4. Fetch-decode-execute cycle

This is the repeating operational cycle of the CPU, executed billions of times per second to run all program code. Examiners frequently ask for step-by-step descriptions of each phase, with marks awarded specifically for correct register references:

1. Fetch phase:

• The memory address of the next instruction stored in the PC is copied to the MAR
• The CU sends a read signal to main memory, and the data at the address in the MAR is copied to the MDR
• The PC is incremented by 1 (or the length of variable-length instructions) to point to the next instruction for the following cycle
• The instruction in the MDR is copied to the CIR for decoding

2. Decode phase: The CU interprets the instruction in the CIR, identifies the operation to be performed, and fetches any required supporting data from memory or registers.
3. Execute phase: The CU sends control signals to the relevant components to complete the instruction. For example, it may trigger the ALU to run an addition, or send a write signal to store a result in memory.

Worked example: For the instruction ADD 8, which adds 8 to the accumulator:

• Fetch: PC holds address 0x002F, copied to MAR. Memory returns ADD 8 to MDR, copied to CIR. PC increments to 0x0030.
• Decode: CU identifies the instruction as "add immediate value 8 to the accumulator".
• Execute: ALU takes the current accumulator value (14) and adds 8 to get 22, stores 22 back in the accumulator. The cycle repeats.

5. Buses — address, data, control

Buses are parallel sets of wires that carry digital signals between the CPU, memory, and I/O devices. All three buses are shared system resources, managed by the CU to avoid conflicting signals:

1. Address Bus: Unidirectional (only carries signals from the CPU to memory/I/O devices). It carries the memory address of the location the CPU wants to read from or write to. The width (number of wires) of the address bus determines the maximum addressable memory of the system: $$\text{Max addressable memory (bytes)}=2^n$$ where $n$ = number of bits in the address bus. For example, a 32-bit address bus can address $2^{32}=4$ GiB of RAM.
2. Data Bus: Bidirectional, carries the actual data being transferred between components. The width of the data bus determines how many bits can be transferred in a single operation: a 64-bit data bus transfers 8 bytes per operation, doubling the throughput of a 32-bit data bus.
3. Control Bus: Bidirectional, carries control signals from the CU to components, and status signals from components back to the CU. Common signals include the read/write flags for memory, interrupt requests from I/O devices, and the system clock signal that synchronises all operations.

Exam tip: A common trap is asking you to calculate maximum addressable memory and providing the data bus width as a distractor. Ignore the data bus width for these calculations: only the address bus width impacts total addressable memory.

6. RISC vs CISC; pipelining intuition

These two architecture and performance topics are frequently tested as 3-5 mark comparison or explanation questions in A-Level Computer Science papers.

RISC vs CISC

Pipelining intuition

Pipelining is a CPU performance optimisation that overlaps the fetch-decode-execute cycles of multiple instructions to increase throughput (number of instructions executed per second). Think of it like a car assembly line: instead of building one car from start to finish before starting the next, each stage of the line works on a different car simultaneously.

For a 3-stage pipeline:

• Without pipelining: 3 instructions take $3\times 3=9$ clock cycles to complete, throughput = 0.33 instructions per cycle
• With pipelining: 3 instructions take $3+2=5$ clock cycles to complete, throughput = ~1 instruction per cycle under ideal conditions

Pipelining does not reduce the time taken to execute a single individual instruction (latency stays the same), it only increases the total number of instructions completed per second. Pipeline stalls occur when an instruction depends on the result of a previous uncompleted instruction, or a branch (if statement, loop) changes the next instruction to be fetched, leaving pipeline stages idle.

7. Common Pitfalls (and how to avoid them)

• Wrong move: Stating that Harvard architecture is used for general-purpose laptops and desktops. Why: Students mix up use cases for the two architecture types. Correct move: Remember Von Neumann is for general-purpose systems, Harvard is for embedded systems, GPUs, and microcontrollers where speed is prioritised over flexibility.
• Wrong move: Confusing MAR and MDR, or PC and CIR functions in the fetch-decode-execute cycle. Why: Students memorise register names without linking them to their purpose. Correct move: Use mnemonics: MAR = Memory Address Register (holds addresses), MDR = Memory Data Register (holds data); PC points to the next instruction to fetch, CIR holds the current instruction being processed.
• Wrong move: Using data bus width to calculate maximum addressable memory. Why: Students assume all bus widths are interchangeable. Correct move: Only address bus width determines addressable memory, use $2^n$ where $n$ is the number of address bus bits. Data bus width only impacts transfer speed per operation, not total memory capacity.
• Wrong move: Claiming pipelining reduces the time to execute a single instruction. Why: Students confuse throughput and latency. Correct move: Pipelining increases throughput (number of instructions per second) by overlapping cycles, but does not change the latency (time per individual instruction).
• Wrong move: Stating RISC is universally better than CISC. Why: Students only learn RISC advantages without considering use cases. Correct move: CISC is preferred for desktops/servers where legacy software compatibility is required, while RISC is preferred for low-power mobile and embedded devices.

8. Practice Questions (A-Level Computer Science Style)

Question 1

(a) State three core features of Von Neumann architecture. [3 marks] (b) Describe one difference between Von Neumann and Harvard architecture, and give one real-world use case for Harvard architecture. [2 marks]

Solution

(a) Any 3 of the following, 1 mark per point:

1. Program instructions and data are stored in the same shared memory space
2. All instructions and data are encoded as binary values
3. Instructions are fetched sequentially from memory for execution
4. A single control unit manages operation via the fetch-decode-execute cycle

(b) Difference: Harvard architecture uses separate, dedicated memory spaces for program instructions and data, while Von Neumann uses a single shared memory space for both (1 mark). Use case: Embedded systems, digital signal processors (DSPs), or GPUs (1 mark).

Question 2

A CPU has a 22-bit address bus and 32-bit data bus. (a) Calculate the maximum addressable memory for this CPU, give your answer in mebibytes (MiB). Show all working. [3 marks] (b) Explain why increasing CPU cache size improves system performance. [2 marks]

Solution

(a) Step 1: Max addressable memory = $2^{22}=4,194,304$ bytes (1 mark). Step 2: 1 MiB = $2^{20}=1,048,576$ bytes (1 mark). Step 3: $4,194,304/1,048,576=4$ MiB (1 mark). No marks are awarded if you use 1000 instead of 1024 for MiB conversion, or use the data bus width in your calculation.

(b) Cache is significantly faster to access than RAM, so storing frequently used instructions and data in cache reduces the number of slow RAM accesses the CPU has to make (1 mark), reducing CPU stall time and increasing overall throughput (1 mark).

Question 3

(a) List the four steps of the fetch phase of the fetch-decode-execute cycle, referencing relevant registers in your answer. [4 marks] (b) Explain what a pipeline stall is, and give one common cause of a stall. [2 marks]

Solution

(a) 1 mark per step, in order:

1. The memory address of the next instruction stored in the Program Counter (PC) is copied to the Memory Address Register (MAR)
2. The Control Unit sends a read signal to main memory, and the data at the address stored in the MAR is copied to the Memory Data Register (MDR)
3. The value in the PC is incremented to point to the address of the next instruction for the following cycle
4. The instruction stored in the MDR is copied to the Current Instruction Register (CIR) for decoding

(b) A pipeline stall is a delay in pipeline execution where one or more pipeline stages are left idle (1 mark). Common causes: data dependency (one instruction requires the result of a previous uncompleted instruction), or branch instructions that change the next instruction to be fetched (1 mark for any valid cause).

9. Quick Reference Cheatsheet

10. What's Next

This topic forms the foundation for several subsequent units in the A-Level Computer Science syllabus, including input/output systems, memory hierarchy, embedded systems, and assembly language programming. A strong understanding of CPU operation and architecture will also help you grasp performance optimisation techniques in later algorithm and programming units, as you will be able to make informed decisions about how code structure interacts with hardware to impact speed and resource use.

If you have any questions about specific concepts, practice question solutions, or want more worked examples tailored to your weak areas, you can ask Ollie the AI tutor at any time via the homepage. You can also find additional practice questions and full past paper walkthroughs for A-Level Computer Science Paper 1 on the OwlsPrep platform to reinforce your learning before your exam.

Aligned with the Cambridge International AS & A Level Computer Science 9618 syllabus. OwlsAi is not affiliated with Cambridge Assessment International Education.