# RISC vs CISC

> Computer Science · CIE A-Level 9618
> Source: https://www.owlsprep.com/study/cie-9618-u4-risc-vs-cisc/

This module compares the two dominant CPU instruction set architectures: Reduced Instruction Set Computer (RISC) and Complex Instruction Set Computer (CISC). We cover key design differences, trade-offs, and real-world applications for CIE A-Level exams.

**Prerequisites:** [Basic CPU structure and instruction set fundamentals](https://www.owlsprep.com/study/cie-9618-u4-cpu-instruction-sets/)

## Learning objectives

- Compare key architectural characteristics of RISC and CISC processors
- Explain core design trade-offs between the two philosophies
- Identify real-world examples of each architecture
- Evaluate suitability for different use cases

## Core Design Principles

RISC and CISC originated from competing approaches to trade-offs between instruction complexity and hardware efficiency. Early computing had limited memory, so CISC was designed to reduce program size by making individual instructions more powerful.

**RISC Design Philosophy** — RISC prioritises simple instructions that execute in a single clock cycle. The goal is to reduce CPI and enable efficient pipelining, with compilers handling more instruction-level work.

*Example:* A RISC ISA splits a complex memory-to-memory add into three separate simple instructions: load, add, store.

CISC, by contrast, builds complex operations directly into the instruction set to reduce the number of instructions a program needs to execute.

**Worked example:** Show how adding two memory-resident numbers would be implemented in RISC vs CISC

1. For CISC, the operation completes in a single instruction that accesses memory directly:
2. $$ADD \quad [M_A], [M_B] \rightarrow [M_C]$$
3. For RISC, all operations must act on registers, so the operation is split into four simple instructions:
4. $$\begin{aligned} \text{LOAD } R1, [M_A] \\ \text{LOAD } R2, [M_B] \\ \text{ADD } R3, R1, R2 \\ \text{STORE } [M_C], R3 \end{aligned}$$

> **Exam tip:** For comparison questions in CIE exams, always structure answers by pairing characteristics for each architecture to get full marks.

## Key Architectural Differences

Beyond core philosophy, RISC and CISC differ in several key hardware and software characteristics that impact overall performance.

| Characteristic | RISC | CISC |
| --- | --- | --- |
| Instruction set size | Small ~100-200 instructions | Large ~200-1000+ instructions |
| Instruction length | Fixed | Variable |
| Average CPI | ~1 | 1-15+ (variable) |
| General purpose registers | Large count (16+) | Smaller count (8-16) |
| Memory access rules | Only load/store access memory | All instructions can access memory |
| Pipelining efficiency | Easy to implement efficiently | More complex due to variable instructions |
| Compiler complexity | More complex | Simpler |

> **tip**
>
> Memory hook: CISC does hard work in hardware, RISC does hard work in software (the compiler).

**Worked example:** Identify which feature is characteristic of RISC: (A) Variable instruction length (B) Single cycle per instruction (C) Direct memory access for arithmetic (D) Small number of registers. State the correct answer and eliminate incorrect options.

1. Correct answer is (B). RISC design prioritises simple instructions that complete in one clock cycle.
2. Eliminate (A): RISC uses fixed-length instructions to simplify pipelining; variable length is a CISC feature.
3. Eliminate (C): Only load/store instructions can access memory in RISC; arithmetic operations only use registers.
4. Eliminate (D): RISC has a large number of general purpose registers to reduce memory access; small register count is CISC.

## Performance and Design Trade-offs

The choice between RISC and CISC depends on performance goals, memory constraints, power consumption, and hardware complexity requirements.

- **RISC benefits**: Lower power consumption, efficient pipelining, higher instruction throughput, simpler hardware
- **RISC drawbacks**: Larger program size, more complex compiler, overhead from splitting complex operations
- **CISC benefits**: Smaller program size, lower memory bandwidth usage, simpler compiler output
- **CISC drawbacks**: Higher hardware complexity, higher power consumption, harder to pipeline efficiently

**Worked example:** Explain why RISC processors are preferred for mobile phones, while CISC is common in desktop PCs

1. Mobile phones prioritise low power consumption and energy efficiency, which aligns with RISC design principles.
2. RISC's simple hardware and efficient pipelining produce less heat and use less battery, a critical requirement for mobile devices.
3. Desktop PCs historically used CISC (x86) to maintain backward compatibility with older software, and benefit from the large memory available in modern systems.
4. Modern desktop CPUs use RISC-like internal micro-operations but retain the CISC instruction set for compatibility, so they are still classified as CISC.

## Real-World Examples & Exam Phrasing

In modern computing, both architectures are widely used for their intended use cases. These are the common examples you are expected to know for CIE exams:

- RISC examples: ARM (all mobile phones, Raspberry Pi), RISC-V, MIPS
- CISC examples: x86/x86-64 (most desktops/laptops/servers), VAX, Intel 80x86

**Worked example:** Name one RISC and one CISC processor example, and state their typical use case

1. RISC example: ARM Cortex-A series
2. Use case: Smartphones and tablets, where low power consumption is a critical requirement
3. CISC example: Intel Core i7 (x86 architecture)
4. Use case: Desktop and laptop PCs, where backward compatibility and general purpose performance are prioritised

**Check your understanding**

Test your understanding of use cases:

1. Which of these processors is a RISC architecture?

   - Intel Core i7
   - AMD Ryzen
   - ARM Cortex-A
   - x86-64

   *Answer:* ARM Cortex-A

   *Why:* Correct: ARM is the most widely used RISC architecture today. Intel and AMD x86 are CISC architectures.

2. Why is RISC suitable for embedded systems?

   - Small program size
   - Low power consumption
   - Complex instructions
   - Backward compatibility

   *Answer:* Low power consumption

   *Why:* Correct: RISC's simple hardware design leads to low power consumption, ideal for battery-powered embedded and mobile systems.

**Exam command terms**

- **Compare RISC and CISC** — You must list at least 3 paired differences (one for each architecture) to get full marks *(Structure your answer as a table or bullet points comparing matching characteristics for each.)*

- **Evaluate why RISC is used in mobile devices** — Explain benefits of RISC for the use case, and mention relevant drawbacks if appropriate *(Always link architectural features to use case requirements: e.g. lower power = longer battery life for mobiles.)*

## Common pitfalls

- **Wrong:** Claiming CISC always has higher performance than RISC because individual instructions are more powerful
  - Why it fails: CPI is much higher for CISC, so overall instruction throughput is often lower than RISC for most workloads
  - Correct: Compare the full trade-off: CISC has lower instruction count but higher CPI; RISC has higher instruction count but lower average CPI
- **Wrong:** Thinking all modern desktop CPUs are pure CISC designs
  - Why it fails: Modern x86 CPUs translate CISC instructions to internal RISC-like micro-operations before execution
  - Correct: Recognise x86 is a hybrid, but still classified as CISC from an ISA perspective for exam purposes
- **Wrong:** Claiming RISC has fewer registers than CISC
  - Why it fails: RISC uses more registers to avoid repeated memory access for operands, a core design feature
  - Correct: RISC has a larger number of general purpose registers than CISC
- **Wrong:** Confusing which architecture requires more complex compiler work
  - Why it fails: Because RISC splits complex operations into multiple simple instructions, the compiler must do more work
  - Correct: RISC = more complex compiler; CISC = simpler compiler

## Cheatsheet

| Characteristic | RISC | CISC |
| --- | --- | --- |
| Instruction length | Fixed | Variable |
| Average CPI | ~1 | Variable 1+ |
| Memory access | Load/store only | Direct for all instructions |
| General purpose registers | Many | Fewer |
| Pipelining efficiency | High | Lower |
| Compiler complexity | Complex | Simple |
| Power consumption | Lower | Higher |
| Common examples | ARM, RISC-V | x86, x86-64 |

## What's next

Understanding RISC and CISC is fundamental to further study of CPU performance, pipelining, and embedded system design. This topic frequently appears in CIE exam questions asking you to compare architectural choices for different computing devices, so always ensure you can link specific design features to performance outcomes and use case requirements. Mastery of this topic also provides a foundation for understanding modern hybrid CPU designs that combine elements of both philosophies.

- [Pipelining](https://www.owlsprep.com/study/cie-9618-u4-pipelining/)
- [Multicore processors](https://www.owlsprep.com/study/cie-9618-u4-multicore-processors/)
- [System software](https://www.owlsprep.com/study/cie-9618-u5-overview/)

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