Instruction Set

Computer Science· Unit 4: Processor Fundamentals, Topic 2· 15 min read

1. Instruction Set Definition and Instruction Format★★☆☆☆⏱ 4 min

📘 Definition

Instruction Set

A complete collection of all machine-level instructions that a processor can execute, defining all possible operations the processor can perform.

Example:

ARM32 has a fixed 32-bit instruction set with around 50 core instructions.

All machine instructions are split into two mandatory components: the opcode (operation code) that defines what action to perform, and one or more operands that define the data or memory location the action acts on.

📐 Worked Example

A 16-bit processor uses a 7-bit opcode. Calculate the maximum number of unique instructions, and how many bits remain for operands.

1
Step 1: The number of unique instructions is equal to $2^{n}$ , where $n$ is the number of bits for the opcode.
2
$2^7 = 128$
3
Step 2: Subtract the number of opcode bits from the total instruction length to get bits for operands:
4
$16 - 7 = 9$
5
Final answer: 128 unique instructions, 9 bits for operands.

Exam tip:

Always double-check if the question asks for number of instructions or number of operand bits, don't mix these up.

2. Classification of Instructions★★☆☆☆⏱ 3 min

Instructions are grouped by their function. Examiners regularly ask to classify given instructions into these core categories:

Data processing (arithmetic/logical): Perform calculations or logical operations on data (e.g., add, subtract, AND, shift)
Data movement: Move data between registers, memory, and I/O (e.g., load, store, move)
Control flow: Change the order of program execution (e.g., branch, jump, call, return)
Input/Output: Communicate with external peripherals

📐 Worked Example

Classify ADD R1, R2, R3, BR MAIN, LOAD R0, [2000] by function.

1
1. ADD R1, R2, R3 adds values from R2 and R3, stores the result in R1. This is a data processing (arithmetic) instruction.
2
1. BR MAIN changes execution flow to the label MAIN. This is a control flow instruction.
3
1. LOAD R0, [2000] copies data from memory address 2000 to R0. This is a data movement instruction.

3. CISC vs RISC Architecture★★★☆☆⏱ 5 min

Comparison of CISC and RISC is one of the most frequently tested topics for instruction sets in CIE 9618. The two architectures have very different design goals:

Methods compared

CISC

Large instruction set, variable instruction length (1-15 bytes), many addressing modes, allows memory-memory operations

+ Pros: Smaller compiled code size, simpler compilers

− Cons: Complex hardware, higher power consumption

RISC

Small simplified instruction set, fixed 32-bit instruction length, few addressing modes, load-store architecture only

+ Pros: Simple hardware, supports efficient pipelining, lower power consumption

− Cons: Larger compiled code size, more complex compilers

📐 Worked Example

Explain why RISC is preferred for modern smartphone processors.

1
Step 1: Smartphones require long battery life, so power efficiency is a key priority.
2
Step 2: RISC has simpler hardware, lower power consumption per instruction, and supports efficient pipelining for higher performance.
3
A full exam answer: RISC processors have lower power consumption, which extends smartphone battery life. Their fixed-length instructions also enable efficient pipelining for better performance.

Exam tip:

For 4-mark comparison questions, always state a matching feature for both architectures to get full marks.

4. Core Addressing Modes★★★☆☆⏱ 4 min

📘 Definition

Addressing Mode

The method used to specify the location or value of the operand of an instruction.

Three core addressing modes are tested most often in CIE 9618:

Immediate addressing: The operand value is stored directly in the instruction, no extra memory access needed.
Direct addressing: The instruction stores the memory address of the operand; the value is retrieved from that memory address.
Register addressing: The operand is stored in a processor register, specified by the instruction.

📐 Worked Example

If R0 initially holds 12, what is the value of R0 after executing ADD R0, #4? Name the addressing mode for #4.

1
Step 1: The # prefix indicates an immediate value, so 4 is stored directly in the instruction.
2
Step 2: Calculate the new value of R0: $12 + 4 = 16$ .
3
Final answer: R0 = 16, addressing mode is immediate addressing.

5. Common Pitfalls

Wrong move:

Only giving one difference between CISC and RISC for a 4-mark question

Why:

Examiners award 1 mark per distinct point, so you will lose marks for insufficient detail

Correct move:

Always prepare at least 3 distinct differences (instruction length, addressing modes, hardware complexity) for comparison questions

Wrong move:

Confusing opcode and operand when calculating maximum number of instructions

Why:

Only the opcode encodes the instruction type, so it is the only part used to count unique instructions

Correct move:

Remember: Opcodes define what the instruction does, so only opcode bits count for calculating unique instructions

Wrong move:

Claiming immediate addressing requires an extra memory access to get the operand value

Why:

Immediate addressing stores the operand value directly in the instruction itself

Correct move:

Only memory-based addressing modes (like direct addressing) require an extra memory access to retrieve the operand

Wrong move:

Classifying load/store instructions as data processing instructions

Why:

Load/store only move data, they do not perform any calculation or processing

Correct move:

Load and store instructions are always classified as data movement instructions

6. Quick Reference Cheatsheet

Feature	CISC	RISC
Instruction Length	Variable	Fixed
Size of Instruction Set	Large (100+)	Small (~50)
Number of Addressing Modes	Many	Few
Architecture	Memory-memory allowed	Load-store only
H	a	r	d	w	a	r	e	C	o	m	p	l	e	x	i	t	y
H	i	g	h
L	o	w

7. Frequently Asked

How many marks do CISC/RISC comparison questions usually have?

They are typically 3-4 mark questions. You get 1 mark per valid distinct point, so always prepare at least 3 differences to get full marks.

Going deeper

syllabusOfficial CIE 9618 SyllabusCheck page 32 for Unit 4 content

What's Next

Instruction set design is foundational for understanding processor performance and pipelining, as RISC's fixed-length instructions enable efficient instruction pipelining to boost throughput. This topic also links closely to assembly language programming and memory hierarchy, two other core high-weight topics for CIE 9618 Paper 4. Mastering the concepts here will help you earn easy marks on multiple common exam questions.