# Addressing Modes

> Computer Science · CIE A-Level
> Source: https://www.owlsprep.com/study/cie-9618-u4-addressing-modes/

This module explains common addressing modes for CPU instructions, how each calculates the effective memory address of data/instructions, and their practical use cases for CIE A-Level 9618 Paper 4.

**Prerequisites:** [Instruction formats and machine language](https://www.owlsprep.com/study/cie-9618-u4-instruction-formats/); [Memory organisation basics](https://www.owlsprep.com/study/cie-9618-u4-memory-organisation/)

## Learning objectives

- Identify different addressing modes used in CPU instruction sets
- Explain the purpose of each addressing mode for common use cases
- Calculate the effective memory address for any given addressing mode
- Select the appropriate addressing mode for a specific programming task

## Immediate and Direct Addressing

**Addressing Mode** — A rule that specifies how the CPU calculates the effective memory address of the target data or instruction from the address field of an assembly instruction.

**Immediate Addressing** — The value to be used by the instruction is stored directly in the instruction itself. No extra memory access is required to retrieve the operand.

*Example:* Used to load constant values into registers.

**Worked example:** Add the immediate value 15 to register R0. State what is stored in the instruction's address field and whether any extra memory access is needed.

1. 1. In immediate addressing, the operand is the value itself, stored directly in the address field.
2. 2. No extra memory access is needed after fetching the instruction, because the value is already embedded in the instruction.
3. Result: The address field holds 15, and 0 extra memory accesses are required.

**Direct Addressing** — The address field of the instruction stores the full effective memory address of the target data. The CPU fetches the data directly from this address in one extra memory cycle.

*Example:* Used to access single fixed memory variables.

**Worked example:** Load the value stored at memory address 1000 into register R1. What value is stored in the instruction's address field?

1. 1. In direct addressing, the address field equals the effective address of the target data.
2. 2. The target data is at address 1000, so the address field stores exactly 1000.
3. Result: Address field value = 1000, 1 extra memory access to retrieve the data.

## Indirect Addressing

**Indirect Addressing** — The address field of the instruction stores the address of a memory location (or register) that holds the full effective address of the target data. Requires multiple memory accesses to retrieve the data.

*Example:* Used for pointers, dynamic data, and accessing large memory spaces.

**Worked example:** An instruction uses memory indirect addressing, with an address field value of 2000. Memory location 2000 stores 5000. What is the effective address of the target data, and how many memory accesses are needed?

1. 1. After fetching the instruction, the CPU first reads the address field value 2000.
2. 2. First extra memory access: retrieve the effective address stored at 2000, which is 5000.
3. 3. Second extra memory access: retrieve the target data from the effective address 5000.
4. Result: Effective address = 5000, 2 extra memory accesses.

> **tip**
>
> Register indirect addressing uses a register instead of memory to store the effective address. This only requires 1 extra memory access, making it faster than memory indirect.

## Indexed Addressing

**Indexed Addressing** — The effective address is calculated by adding a constant base offset (stored in the instruction) to the value held in a dedicated index register.

*Example:* The most efficient mode for accessing elements of an array.

**Worked example:** An array starts at base address 200. Access the 3rd element (0-indexed, index = 2). Index register X holds 2. Calculate the effective address.

1. 1. The formula for effective address in indexed addressing is:
2. $$EA = \text{Base Offset} + \text{Index Register Value}$$
3. 2. Substitute the given values: Base Offset = 200, Index Register Value = 2.
4. 3. Calculate: $EA = 200 + 2 = 202$.
5. Result: The effective address of the 3rd array element is 202.

> **info**
>
> To loop through an array with indexed addressing, you only increment the index register each iteration. The instruction's base offset never needs to change, making loops very efficient.

## Relative Addressing

**Relative Addressing** — The effective address is calculated by adding an offset value (stored in the instruction) to the current value of the Program Counter (PC).

*Example:* Used for branching and jumping to nearby instructions.

**Worked example:** The current branch instruction is stored at address 100, and is 4 bytes long. After fetching the instruction, the PC holds 104. The branch offset is +12. Calculate the effective address of the branch target.

1. 1. The formula for effective address in relative addressing is:
2. $$EA = PC + \text{Offset}$$
3. 2. Recall that after fetching an instruction, the PC is automatically updated to point to the next instruction, so we use this updated PC value.
4. 3. Substitute values: $EA = 104 + 12 = 116$.
5. Result: The branch target is at effective address 116.

> **tip**
>
> Relative addressing enables position-independent code: the entire program can be moved to a different memory location without modifying branch instructions, since offsets are always relative to the current PC.

## Common pitfalls

- **Wrong:** Confusing immediate and direct addressing, assuming the value in the address field is always an address.
  - Why it fails: Immediate addressing uses the address field value as the actual operand, not an address.
  - Correct: Check if the instruction needs a constant value (immediate) or data from memory (direct).
- **Wrong:** Using the address of the current instruction for relative addressing calculations.
  - Why it fails: The PC is updated to point to the next instruction before calculating the effective address, so this gives the wrong offset.
  - Correct: Always add the offset to the updated PC value (current instruction address + instruction length).
- **Wrong:** Claiming memory indirect addressing only needs one extra memory access.
  - Why it fails: One access is needed to retrieve the effective address, a second to retrieve the actual data.
  - Correct: Count 2 extra memory accesses for memory indirect addressing, 1 for register indirect.
- **Wrong:** Using the index value as the full effective address for array access with indexed addressing.
  - Why it fails: Students forget to add the array's base address stored as the instruction offset.
  - Correct: Always add the base offset of the array to the index register value to get the effective address.
- **Wrong:** Claiming immediate addressing requires an extra memory access to get the operand.
  - Why it fails: The operand is embedded directly in the instruction itself, so no extra access is needed.
  - Correct: Immediate addressing requires 0 extra memory accesses after fetching the instruction.

## Cheatsheet

| Addressing Mode | Effective Address | Extra Memory Accesses | Common Use Case |
| --- | --- | --- | --- |
| Immediate | Value stored in instruction | 0 | Loading constants |
| Direct | EA = Address field value | 1 | Accessing fixed variables |
| Memory Indirect | EA = Value at (Address field) | 2 | Accessing pointers/dynamic data |
| Indexed | EA = Base offset + Index register | 1 | Accessing array elements |
| Relative | EA = Updated PC + Offset | 0 | Branching/jumps |

## What's next

Addressing modes are a core component of CPU instruction set design, and understanding them is key to interpreting assembly instructions, explaining CPU memory access behaviour, and answering common exam questions on processor fundamentals for CIE 9618. This topic builds on your existing knowledge of instruction formats and memory organisation, and forms the foundation for working with assembly programming and understanding how the CPU interacts with memory during instruction execution. Addressing mode questions appear regularly in both multiple-choice and extended response sections of Paper 4, so mastering effective address calculations for each mode is critical for exam success.

- [RISC vs CISC](https://www.owlsprep.com/study/cie-9618-u4-risc-vs-cisc/)
- [Pipelining](https://www.owlsprep.com/study/cie-9618-u4-pipelining/)
- [Multicore processors](https://www.owlsprep.com/study/cie-9618-u4-multicore-processors/)

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